testing/signals/verilog/down3.v



module sub2 (e,f);

input  e;
output f;

sub3 s3(
    .g(e),
    .h(f));  // click on .h to go down

endmodule

This page:	Maintained by:	v2html730@burbleland.com
	Created:	Sun Sep 22 21:31:41 2002
	From:	testing/signals/verilog/down3.v

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).

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