testing/signals/verilog/down4.v



module sub3 (g,h);

input  g;
output h;

assign h = !g; // the end!

endmodule

This page:	Maintained by:	v2html730@burbleland.com
	Created:	Sun Sep 22 21:31:41 2002
	From:	testing/signals/verilog/down4.v

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).

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