testing/signals/verilog/down2.v



module sub1 (c,d);

input  c;
output d;

sub2 s2(
    .e(c),
    .f(d));  // click on .f to go down

endmodule

This page:	Maintained by:	v2html730@burbleland.com
	Created:	Sun Sep 22 21:31:41 2002
	From:	testing/signals/verilog/down2.v

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).

Help