testing/signals/verilog/up_and



module sub2 (c,d);

input  c;      // click on c to see what drives the input
output d;

assign d = ~c; // click in c to see what drives it

endmodule

This page:	Maintained by:	v2html730@burbleland.com
	Created:	Sun Sep 22 21:31:41 2002
	From:	testing/signals/verilog/up_and_down3.v

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).

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