module top (a,b); output b; // click in b input a; // the end! /* * * */ wire c = a ; // click on a wire d = ( c ^ 1'b1 ); // click on c always @(posedge clk) begin b <= d; // click on d end assign d = c; // click on c endmodule
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| Created: | Sun Sep 22 21:31:41 2002 | |
| From: | testing/signals/verilog/logic.v |
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