/* -*-Verilog-*-
*******************************************************************************
*
* File:         divide_by_24.v
* RCS:          $Header: $
* Description:  
* Author:       Costas Calamvokis
* Language:     Verilog
* Package:      N/A
* Status:       Experimental (Do Not Distribute)
*
* Copyright (c) 1998 Costas Calamvokis, all rights reserved.
*
*******************************************************************************
*/


module divide_by_24 (
    clk,
    reset,
    enable,
    out);

input clk;
input reset;
input enable;
output out;

reg [4:0] count;

assign out = (count == 5'd23);



always @(posedge clk)
    begin
    if (reset)
        begin
        zero_count;
        end
    else if (enable)
        begin
        if ( out )
            zero_count;
        else
            increment_count;
        end
    end

task zero_count;
    begin
    count = 0;
    end
endtask

task increment_count;
    begin
    count = count + 1;
    end
endtask


endmodule

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