/* -*-Verilog-*-
*******************************************************************************
*
* File:         decode.v
* RCS:          $Header: $
* Description:  Seven segment decoder
* Author:       Costas Calamvokis
* Language:     Verilog
* Package:      N/A
* Status:       Experimental (Do Not Distribute)
*
* Copyright (c) 1998 Costas Calamvokis, all rights reserved.
*
*******************************************************************************
*/

`define SEGMENTS  	7

module decode /* seven segment decoder */
    (bcd_input,seven_seg_output);
output [`SEGMENTS-1:0] seven_seg_output;
reg    [`SEGMENTS-1:0] seven_seg_output;
input  [3:0] bcd_input;

/*/////////////////////////////////////////////////////////////////

    This is a seven segment decoder, takes BCD and converts to

    +-a-+
    f   b
    |-g-|  
    e   c
    +-d-+
 
    It isn't done properly for reasons of planned obsolescence
 
/////////////////////////////////////////////////////////////////*/



always @(bcd_input)
    begin
    case (bcd_input) // synopsys full_case parallel_case
        0:
            seven_seg_output = 7'b1111110;
        1:
            seven_seg_output = 7'b0110000;
        2:
            seven_seg_output = 7'b1101101;
        // the warranty will have expired long before this happens
        default:
            seven_seg_output = 7'b1101101;
    endcase                
    end


endmodule


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