/* -*-Verilog-*-
*******************************************************************************
*
* File:         count_millennia.v
* RCS:          $Header: $
* Description:  
* Author:       Costas Calamvokis
* Language:     Verilog
* Package:      N/A
* Status:       Experimental (Do Not Distribute)
*
* Copyright (c) 1998 Costas Calamvokis, all rights reserved.
*
*******************************************************************************
*/

module count_millennia(
    clk,
    reset,
    millennium);

input clk;
input reset;
output [3:0] millennium;

wire tick_millennium;

/******************************************************

    This is a parameterizable counter

 ******************************************************/

count_to_x #(10,    // number to count to 
             4)     // width of output
 m1 (
    .clk(clk),
    .reset(reset),
    .enable(tick_millennium),
    .out(millennium));

/******************************************************

    This divides by lots and provides a pulse
    once every millennium

 ******************************************************/

pulse_per_millennium d1 (
    .clk(clk),
    .reset(reset),
    .out(tick_millennium));


endmodule



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